1. Field of the Invention
The invention relates generally to an architecture for host I/O adapters as generally practiced in present computing workstations and personal computers and relates more specifically to a master/slave configuration architecture that provides enhanced flexibility for adding I/O channel capabilities to an I/O adapter without requiring additional host I/O slots.
2. Description of Related Art
Present day computing workstations and personal computers (collectively referred to herein as xe2x80x9cPCsxe2x80x9d) interact with peripheral I/O devices through host I/O adapters. Typically, a PC includes an I/O interface bus into which host I/O adapters applied. ISA, EISA, PCI, and others are exemplary of such I/O interfacing buses commonly used in present day PCs. Host adapter cards are plugged into the I/O interface bus and adapt signals from the host I/O interface bus to appropriate signal values for the particular peripheral I/O device or devices attached to the host adapter. For example, a SCSI host adapter plugs into the I/O interface bus of its host PC and provides connection to a SCSI bus on which one or more peripheral I/O devices are attached. Similarly, a fiber Channel host adapter plugs into a slot in the I/O interface bus up its host PC and provides a connection for that PC to a fiber Channel communication medium. Such adapters converge signals from, for example, a PCI I/O interface bus into appropriate signals for the SCSI bus or fiber Channel communication medium and vice versa.
Host adapters as presently known in the art generally include significant processing power to permit the host adapter to perform substantial processing of I/O transactions thereby offloading the processing capabilities of the host PC. Often a host adapter will include a general purpose microprocessor as well as one or more special-purpose I/O channel processors for coupling the adapter to the host I/O interface bus and for coupling the adapter to the I/O peripheral devices (such as SCSI, USB, Ethernet, Fibre Channel, etc.). A single host adapter may include multiple such special-purpose I/O channel processors to permit connection of additional I/O peripheral devices. For example, a single SCSI host adapter may have a single special-purpose I/O channel processor for connection to a host PC PCI bus and multiple special-purpose I/O channel processors for connecting the host adapter to multiple SCSI buses.
Regardless of the number of such special-purpose I/O channel processors for connection to I/O peripheral devices (often referred to as xe2x80x9cI/O channelsxe2x80x9d), present day host adapters have some fixed limit to the number of I/O channels supported by the host adapter interface card. To provide additional I/O channel connections for the host PC, additional duplicate host adapters must be added to the host PC. Each such additional duplicate host adapter utilizes another slot in the host PCI""s interface bus. For example, a single SCSI host adapter may provide connections for one or two SCSI interface peripheral buses. To provide additional connections for a host PC to SCSI interface peripheral buses, additional host adapters must be addedxe2x80x94each utilizing an additional PCI I/O interface bus slot in the host PC.
Each additional host adapter added to a host PC utilizes an additional slot in the I/O interface bus of the host PC and, in turn, utilizes additional resources within the host PC (i.e., computing resources such as I/O addresses and interrupt IRQs). It is evident from this discussion that a need exists for an improved I/O adapter architecture that permits flexible expansion of I/O channels supported by the host I/O adapter without a over utilizing host PC resources such as I/O interface bus slots and other I/O related computing resources.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing a host I/O adapter architecture that utilizes a master/slave configuration. A host adapter in accordance with the present invention is designated as a master device (also referred to herein as master host adapter or master I/O processor) and includes all processing features of a host adapter as presently known in the art. In addition, the master host adapter of the present invention includes a slave port interface support to communicate with a slave I/O processor. The slave I/O processor of the present invention is a dramatically simplified device relative to the master host adapter. The slave I/O processor includes additional special-purpose I/O channel processors to provide additional I/O channels for the master I/O processor. The slave I/O processor also includes a master port interface to connect to the master I/O processor through its slave port interface. A master/slave bus connects the slave port interface of the master I/O processor and the master port interface of the slave I/O processor to permit communications between the master I/O processor and slave I/O processor. Notably, the slave I/O processor is preferably devoid of a general purpose microprocessor and host bus interface ports. Further, the slave I/O processor is preferably substantially devoid of memory associated with the general purpose microprocessor of the master I/O processor.
The master/slave I/O processor architecture of the present invention permits addition of I/O channels to the master I/O processor without utilizing an additional host PC I/O interface bus slots and associated computing resources in the host PC. In a first preferred embodiment, slave I/O processors are connected to the master I/O processor in a xe2x80x9cdaughter boardxe2x80x9d physical configuration. In alternative embodiments, the slave I/O processor may be physically mounted remote from the master I/O processor with appropriate interconnect cabling serving as the master/slave bus for communications between the master I/O processor and slave I/O processor. In all embodiments, the slave I/O processor imposes no burden on the resources of the host PC in that it is not required to be mounted in a host PC I/O interface bus slot and does not consume any related I/O resources of the host PC. Further, the slave I/O processor is substantially simpler than the master I/O processor to thereby reduce the cost of adding he additional I/O channels in a host PC.
The present invention is particularly well-suited for interfacing a PCI bus in a host computer with multiple SCSI or Fibre Channel I/O peripheral buses connected to peripheral components such as data storage subsystems.
The above and other aspects, features, and advantages of the present invention will become apparent from the following description and the attached drawings.